In the electronics industry, there is a need for apparatus of smaller size, higher performance, and higher memory storage. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions and increasing the number of layers of such devices on a chip. In order to accomplish such high device packing densities, smaller and smaller features sizes are required. This may include the thickness of the wafer, the width and spacing of interconnecting lines, spacing and diameter of contact holes, the surface geometry of various features, and the like.
The process of manufacturing semiconductors or integrated circuits (commonly called ICs or chips) typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. Integrated circuit devices are typically fabricated on the thin wafers of silicon. Typically, after fabrication of the integrated circuit devices on the front surface of the wafer, the wafer is thinned to reduce the cross section of the wafer using a mechanical and/or chemical grinding process or etching.
After thinning the wafer, the wafer is generally sawn or diced into rectangularly shaped “dice” along two mutually perpendicular sets of parallel lines or streets separating each row and column of dice in the wafer. Thus, the individual integrated circuit semiconductor die in the form of semiconductor dice are singulated from the wafer. The die having functional devices may be packaged and further tested to ensure that each packaged device satisfies a minimum level of performance. Typically, the functional devices are attached to a substrate and packaged by encapsulating the die in a plastic package. Packaging of the functional devices facilitates handling of the devices and also protects the singulated die from damage during the manufacture of modules using the packaged devices.